Chip techniques block power leakage

By Kimberly Patch, Technology Research News

A big push in the computer industry is to figure out ways to design chips so they use less power, which will allow for portable devices that run longer and use lighter batteries.

Researchers at Purdue University have designed architecture changes that allow a computer chip to dynamically turn off unneeded portions of instruction caches. The Dynamically Resizable i-cache architecture reduces the average cache size applications need by 62 percent, according to the researchers' numbers.

At the same time, the researchers have modified memory circuits so that voltage for unused memory cells can be turned off, stopping leakage in unused cache segments and saving energy. Leakage is simply current flowing in a circuit that is not being used. "When there's no activity in the circuit there's [still] a current flowing through the devices and that is unwanted leakage current," said Kaushik Roy, professor of electrical engineering at Purdue.

The combination of architecture changes and the Gated-Vdd memory circuits reduces cache leakage by as much as 100 times, said Roy. The lower leakage, in turn, allows for the use of lower-threshold transistors, which typically leak more power, but increase the performance of the chip.

As time goes on, leakage will loom larger as a potential problem, said Roy. A typical chip draws 12 watts and leaks, or loses, about 12 to 15 percent of that power. But because leakage is an exponential function of power, as transistors get smaller, the leakage percentage will rise, Roy said. "Transistors inherently will have higher leakage as you scale down the device sizes. This is going to be more and more important in future technologies," he said.

The architecture change allows the chip to dynamically change the size of instruction and data caches based on what a program needs at any given moment. It does this by monitoring requests the chip makes for information from a cache. "[It] monitors the miss rate of the cache and based on that decides whether within a particular application sections of the cache can be turned off," said Roy.

The monitoring reduces performance by two to four percent. However, this is more than made up for by the use of lower-threshold transistors, he said.

The circuit-level change to the chip involves an extra transistor for every few memory cells, which are themselves made up of hundreds of transistors. It works out to about one extra transistor per 1000, said Roy. The extra transistor essentially blocks current to unused portions of cache. This is done through "a stacking effect where you get a negative gate source voltage for some of the transistors and that reduces the leakage exponentially," he said.

"I think what they're doing is good stuff," said David Albonesi assistant professor of electrical and computer engineering at the University of Rochester. "If you talk to people like Intel, leakage is a concern. People are trying to address it in various ways. What [they] have is a pretty novel way to handle this [using] circuits and using architecture. In the past what we've done is circuit level approaches," Albonesi said.

Their approach works out to "a very small performance hit potentially for a large impact on leakage," he added.

Next, the researchers plan to use similar architectural changes to try to cut down on overall power use. "We're looking at cache organizations and were also looking at use of different kinds of voltage," said Roy.

The gated Vdd and Dynamically Resizable i-cache designs could be implemented within a few months, said Roy.

Roy's research colleagues were Se-Hyun Yang, Michael Powell, Babak Falsafi and T. N. Vijaykumar, all of Purdue University. The researchers presented their work in a paper at the International Symposium on Low-power Electronics and Design in Rapallo, Italy in July.

The research was funded by the Semiconductor Research Corporation, a consortium of companies that includes IBM, Intel, HP, Lucent and Texas Instruments, among others.

Timeline:   < 1 year
Funding:   Corporate
TRN Categories:   Architecture; Integrated Circuits
Story Type:   News
Related Elements:  Technical paper "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories," International Symposium on Loan Power Electronics and Design, Rapallo, Italy, July 25-27, 2000


November 15, 2000

Page One

Biometrics takes a seat

Oversize oddity could yield quantum computers

Switch narrows molecular-macroscopic gap

Tiny metal wires chart nanoelectronics

Chip techniques block power leakage


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