Memory stores three bits in one

By Eric Smalley, Technology Research News

The usual way to cram more storage capacity into memory chips is to shrink the bits that hold the 1s and 0s of computer information. An alternative is to put multiple bits in the same spot, an approach researchers are looking to now that making ever smaller electronic devices has become increasingly difficult.

Researchers from the University of Southern California and NASA have built a prototype molecular memory device that stores three bits in the same spot. "We can store three bits of information in one memory cell," said Chongwu Zhou, an assistant professor of electrical engineering at the University of Southern California. "This multiplies the storage density without increasing the device footprint."

A memory chip based on the researchers' prototype would be able to hold 40 gigabits, which is a little more than a DVD's-worth of data, per square centimeter, and the method has the potential to hold 10 times that. Today's flash memory chips hold of about 1 gigabit per square centimeter.

The multilevel molecular memory could be used to make memory chips for computers and cameras, said Zhou. The devices could also be made on flexible substrates, which means they could be used in smart cards, he said.

The researchers' prototype retained data for 600 hours, which is considerably longer than previous prototype molecular memory devices, said Zhou.

Each memory cell consists of a field-effect transistor made from a 10-nanometer-diameter indium oxide wire. Current applied to a gate electrode produces an electric field around the nanowire, which lowers the nanowire's electrical resistance, allowing current to flow through the nanowire. A nanometer is one millionth of a millimeter, or the span of 10 hydrogen atoms.

The nanowire in the memory cell is covered in molecules of an organic compound that adjust the nanowire's electrical conductance to eight discrete levels. These levels represent the eight possible combinations of three bits: 000, 001, 010, 011, 100, 101, 110 and 111.

The molecules undergo an oxidation/reduction, or redox, reaction in the presence of an electrical current. Redox reactions change the structure of molecules by adding or removing one or more electrons. Oxidation removes electrons and reduction adds electrons.

Applying a negative voltage to the nanowire writes data to the memory cell, and the amplitude, or strength, of the voltage determines the degree of the redox reaction, which in turn determines the nanowire's conductance level. Data stored in the memory can be read by measuring the conductance levels. The memory can be erased with a large positive voltage.

The researchers' prototype transistor would provide a data density of 40 gigabits per square centimeter, said Zhou. "If we scale down the nanowire length by a factor of 10 to 200 nanometers, the density can approach 400 gigabits per square centimeter," he said.

The multilevel molecular memory could be used practically in 5 to 10 years, said Zhou. "Substantial development work is needed to push the performance even further and to develop a fabrication process amenable for mass production," he said.

Zhou's research colleagues were Chao Li, Bo Lei, Daihua Zhang, Song Han, Tao Tang, Xiaolei Liu and Zuqin Liu of the University of Southern California, and Wendy Fan, Sylvia Asano, Meyya Meyyappan and Jie Han of NASA. They published the research in the March 15, 2004 issue of Applied Physics Letters. The research was funded by the National Science Foundation (NSF) and NASA.

Timeline:   5-10 years
Funding:   Government
TRN Categories:   Biological, Chemical, DNA and Molecular Computing; Nanotechnology; Data Storage Technology
Story Type:   News
Related Elements:  Technical paper, "Multilevel Memory Based on Molecular Devices," Applied Physics Letters, March 15, 2004


May 5/12, 2004

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