Nano memory scheme handles defects

September 8/15, 2004

Electrical components that are two or three orders of magnitude smaller than E. coli bacteria promise ultra-high speed at ultra-low-power, but they also present several challenges. Nanoscale electronics devices have a fairly high defect rate, and architectures designed to guide their use must take this into account

Researchers from Hongik University in Korea have devised a memory architecture designed for nanoscale crossbar electronics.

The technique addresses the problem of defects in molecular memory without significantly disrupting existing molecular memory architectures such as that demonstrated by Hewlett-Packard labs, according to the researchers.

Key to the architecture is a traditional layer of electronics that keeps track of defects and performs address translation in order to work around the defects in the molecular part of a chip.

Because of the high rate of defects in molecular crossbar electronics, redundant components are needed to make practical memory devices. This reduces the benefit of using molecular components. The researchers' addressing scheme requires 22 percent of the chip areas taken up by redundant components in existing redundancy schemes, according to the researchers.

The hybrid chip may be a stepping stone from traditional electronics to fully molecular electronics, according to the researchers.

In order for the architecture to be practical, a reliable interface between the molecular layer and the larger but still microscopic traditional electronics layer must be made, according to the researchers.

It could be 10 years before molecular memory is practical, according to the researchers. The work appeared in the August 2, 2004 issue of Nanotechnology.

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