Tinier transistors keep Moore's Law on track

By Kimberly Patch, Technology Research News

A pair of research teams have independently shown that similar design modifications would allow transistors to be made as small as 10 nanometers, taking Moore's Law to about the year 2025.

Moore's Law says the number of transistors that can be crammed onto a computer chip doubles every 18 months. It is a prediction that computer chips have followed since they were invented around 1960. At several points in the past few decades, researchers have worried that this doubling, and the accompanying increase in chip speed, would slow as it finally hit up against the laws of physics.

Conventional wisdom says that it's likely to happen sometime within the next decade as the path electrons take through a transistor shrinks from today's state-of-the-art 100 nanometers to something less than 50 nanometers long.

This is because when presented with a channel less than about 50 nanometers, electrons are able to act like waves as well as particles and tunnel through it, continuing the flow of current whether or not the transistor is turned on.

The research teams, however, have concluded that double-gate field effect transistors (FET's) can block the flow of electrons in channels as short as 10 nanometers. University of California at Berkeley researchers have fabricated working, double-gate transistors as small as 15 nanometers.

A transistor usually has three gates -- a pair of gates serve as the entrance and exit for the electron flow, and the third gate is a switch. Voltage flowing through the third gate opens the channel to electron flow, while turning off the voltage blocks electron flow in the channel. Double-gate transistors have four gates, and use gates positioned both above and below the channel to control the flow of electrons.

The gates effectively surround the channel with an electric field, which blocks electrons from tunneling through the channel until the distance between the entrance and exit gates shrinks to about 10 nanometers.

"The idea is to try to surround the conducting layer as much as possible," said Mark Lundstrom, a professor of electrical and computer engineering at Purdue University. "Putting a gate both on the top and bottom gives you a very strong electrostatic field that can block the flow of electrons between the other two terminals," he said.

The process is analogous to stopping blood from flowing in a vein, said Tsu-Jae King, an associate professor of engineering and computer sciences at the University of California at Berkeley and director of its microfabrication laboratory. "It is easier to stop blood flow if you pinch the vein from both sides, rather than to press it only from one side."

The Purdue team used tools designed to measure the electronics of molecules to figure out just how small the double-gate transistors could go. "What we've done is taken the theoretical framework that's used to explain experiments on conduction of molecules and applied [it] to transistors so we can really have a quantum-scale simulation that can address the problem [of] how small a transistor can be," said Lundstrom.

The simulation showed that the double gate would block tunneling down to about 10 nanometers, he said. In addition, because applications that do not require low power can likely tolerate a small amount of electron leakage through tunneling, they could potentially use transistors as small as eight nanometers, he said.

The industry will hit up against a size barrier using traditional transistors in five to seven years, Lundstrom pointed out. That leaves enough time to work out the trickier manufacturing process for the double-gate transistors, he said.

The manufacturing process that produces silicon devices usually starts with a piece of silicon and builds layers on it. "The tough part is figuring out the three-dimensional processing flow that can be used to put a gate on the bottom," said Lundstrom.

Although further optimization of the materials and the fabrication process is needed, the Berkeley team's basic design shows that it is possible to manufacture "high-performance sub-20 nanometer" transistors, said King.

The Purdue simulation is available for scientists and designers to use, said Lundstrom. "A lot of the commercial... computer-aided design tools don't take into account quantum phenomena. So we posted this on a web page so [they] can run those commercial tools on the simulation and compare the results," he said.

Lundstrom's research colleagues are Zhibin Ren, Ramesh Venugopal and Supriyo Datta of Purdue University, Dejan Jovanovic of Motorola and Los Alamos National Laboratory. The research was funded by Semiconductor Research Corp. (SRC) and the Defense Advanced Research Projects Agency (DARPA).

King's research colleagues are Jakub Kedzierski, Peiqi Xuan and Chenming Hu of UC Berkeley, Erik H. Anderson of Lawrence Berkeley National Laboratory, and Jeffrey Bokor of UC Berkeley and Lawrence Berkeley National Laboratory. The research was funded by DARPA.

Both groups presented their research at the International Electron Devices Meeting in December, 2000 in San Francisco.

Timeline:   5-7 years
Funding:   Corporate, Government
TRN Categories:   Integrated Circuits
Story Type:   News
Related Elements:  Technical papers, "The Ballistic Nanotransistor: A Simulation Study," and "Complementary Silicide Source/Drain Thin-Body MOSFETs for the 20nm Gate Length Regime," presented at the International Electron Devices Meeting (IEDM), December 11-16, 2000 in San Francisco; Purdue simulation, available at www.nanohub.purdue.edu.


December 20/27, 2000

Page One

Tiny wires store more

Tinier transistors keep Moore's Law on track

3-D geometry adds twists to microfabrication

Virtual annotation fosters understanding

Silicon process produces pockets


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